1. Field of the Invention
This invention relates to the means of reducing ESD damage to integrated circuits (ICs) comprising a substrate carrying a large number of circuit elements such as transistors and the like.
2. Prior Art
It is well known that ICs are subject to serious damage or destruction as a result of Electrostatic Discharge (ESD) events. The electrostatic charge can be developed by any of many sources, such as lightning, friction between insulating bodies such as synthetic fiber clothing, and contact with chip handling apparatus. Damage occurs when the ESD charge is accidentally coupled to one of the circuit terminal points to cause a large pulse of current to flow through some portion of the metal interconnect of the chip to a sensitive circuit element of the IC. Frequently, such current pulses will destroy the circuit element and with it the entire IC chip.
Bipolar junctions, dielectrics and thin film circuit elements (i.e., thin film resistors, diffused resistors, dielectric isolations, oxide capacitors) are especially subject to damage from ESD transients of relatively high energy. Such ESD transients can be simulated by the so-called Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM).
Various devices have been employed to prevent damage to ICs from ESD events. For example, individual circuit elements often are protected by additional devices which shunt the ESD energy and thereby protect the element in question. In general, a separate shunt device must be provided for each element requiring protection (although in some cases the protection device may be shared by more than one element requiring protection). In any event, providing protection devices to prevent damage from ESD events requires additional IC area and typically produces some harmful side effects such as additional parasitic capacitance which slows down the response time of the circuitry. It is very desirable to reduce the impact of these detrimental consequences resulting from the use of ESD protective devices. Additionally, to fabricate the ESD device, it is desirable to use standard fabrication sequences which are monitored and controlled by statistical means.